Surface Acoustic Wave (SAW) filters are used in many applications such as Radio Frequency (RF) filters. For example, SAW filters are commonly used in Second Generation (2G), Third Generation (3G), or Fourth Generation (4G) wireless transceiver front ends, duplexers, and receive filters. The widespread use of SAW filters is due, at least in part, to the fact that SAW filters exhibit low insertion loss with good rejection, can achieve broad bandwidths, and are a small fraction of the size of traditional cavity and ceramic filters. Usually, SAW filters use resonators at the surface of a piezoelectric crystal. The resonators may be coupled electrically to form a so-called impedance element filter or ladder filter. They may also be coupled acoustically by inserting several transducers between two reflectors, in which case, they form a Coupled Resonator Filter (CRF), also sometimes called a Double Mode SAW filter (DMS). Hybrid architectures that cascade CRF stage and ladder stages may be used. The performance of the filter is depending on the individual resonators characteristics.
Several parameters are important for a SAW resonator. One important parameter is the effective piezoelectric coupling factor (K2), which depends on the ratio between antiresonance and resonance frequency. SAW resonators with larger coupling factors have larger frequency shifts between resonance and antiresonance and can be used to design wide-band filters. The coupling factor mostly depends on the chosen piezoelectric substrate. Larger K2 make possible the design of filters with a larger fractional bandwidth. Another important parameter of a SAW resonator is the resonator Quality Factor (Q), which influences the insertion losses of a filter designed with the SAW resonator and the steepness of the filter response. Q depends mostly on the acoustic and electric losses in the SAW resonator.
Also, the resonance frequency of a SAW resonator is proportional to the velocity of the SAW. When the temperature changes, the velocity of the wave changes, and the filter shifts in frequency. Additionally, due to thermal expansion, the component dimensions change, leading also to an additional frequency shift. SAW filters need to be able to select a frequency band for a temperature range that is typically a range of 100° Celsius (C) or more. A large thermal sensitivity of the center frequency of a SAW filter results in a filter response shifting in frequency and overall in degraded performances inside a given temperature range. The thermal sensitivity is measured by a coefficient, Most materials have a negative TCF, meaning that the frequency decreases when the temperature increases.
SAW filters using leaky surface waves have losses due to the radiation of acoustic energy into the bulk substrate. One approach to reduce these losses is to use a piezoelectric film at the surface of a support substrate. For example, guided SAW devices have a layered substrate where a piezoelectric layer is bonded or deposited on (e.g., directly on) the surface of a support, or carrier, substrate. If the acoustic velocity of the support substrate is larger than the acoustic velocity in the piezoelectric film, the acoustic wave is guided inside the film and the losses into the bulk are suppressed. This approach is beneficial only if the piezoelectric film is thin enough. If a thick film is used, several spurious modes, due to higher order modes in the film, exist. Relatively thick films (10 wavelengths or so) may be used to improve the temperature sensitivity but do not provide a significant reduction of the losses.
An improvement on this approach, which is described in the co-filed and commonly-owned patent application U.S. Patent Applications entitled “GUIDED SURFACE ACOUSTIC WAVE DEVICE PROVIDING SPURIOUS MODE REJECTION” and which discloses a bonded wafer comprising a piezoelectric layer over a non-semiconductor substrate, is to use piezoelectric thicknesses thinner than one or two wavelengths, which provides suppression of the bulk radiation losses with a limited or no spurious generation. It was discovered that using this technique raised new challenges, however, when used with a semiconductor substrate: if the support substrate is a semiconductor like silicon, the quality factor is limited by a parasitic conductance inside the substrate. This is illustrated in FIGS. 1A and 1B, which are not drawn to scale.
FIG. 1A shows a cross-section view of a SAW device constructed on a conventional bonded wafer 10 having a piezoelectric layer 12 of thickness TOLD over a silicon substrate 14 having a top surface 16. An array of electrodes 18 (only some of which are shown), referred to herein in singularly as the electrode 18 and in plurality as electrodes 18, form electrical connections to the top surface of the piezoelectric layer 12. A parasitic capacitance C exists between electrodes 18 and the silicon substrate 14. FIG. 1A shows a conventional bonded wafer having a thick piezoelectric layer 12, e.g., TOLD is typically more than 10˜15 times lambda (λ), which is the wavelength of the center operating frequency of the SAW device and is twice the period of the electrodes, where the “period” is the center-to-center distance between two adjacent electrodes. Due to the bulk resistance of the silicon substrate 14, an inherent resistance R exists within the top surface 16 between parasitic capacitors C. Due to the thickness of the piezoelectric layer 12, the value of C is small and therefore the effect of R on the performance of the device is negligible.
FIG. 1B shows a cross-section view of a SAW device built on a bonded wafer 20 having a very thin piezoelectric layer 12 having a thickness TNEW, located above the silicon substrate 14. Compared to the conventional bonded wafer 10, the bonded wafer 20 has a larger parasitic capacitance, C′, due to the relative thinness of the piezoelectric layer. It was also discovered that, for a semiconductor substrate such as silicon substrate 14, if TNEW is less than ˜2λ, an inversion layer appears, shown in FIG. 1B as the line of electrons or charges located at the top of the silicon substrate 14.
The presence of these additional charges creates a parasitic conductance that reduces the resistance between the capacitors—i.e., the value R′ of the bonded wafer 20 is lower than the value of R within the conventional bonded wafer 10—due to the parasitic conductance. The quality factor Q of a SAW filter is affected by R′: as the resistance R′ goes down, the filter's quality factor drops.
FIGS. 2A and 2B are graphs illustrating the effect that a parasitic channel has on admittance/conductance and Q, respectively, for the bonded wafer 20. In FIGS. 2A and 2B, the solid line represents the performance of the device when the parasitic channel is absent, while the dotted line represents the performance of a device when a parasitic channel is present. When the thickness of the piezoelectric layer is thinner, the influence of the transducer on the silicon substrate becomes larger and the reduction of the quality factor becomes significant. FIGS. 2A and 2B illustrate the effects of a parasitic channel when the piezoelectric layer 12 has a thickness T=0.5λ. In FIG. 2A, it can be seen that the presence of the parasitic channel increases the conductance at antiresonance. In FIG. 2B, it can be seen that the presence of the parasitic channel reduces the quality factor Q drastically.
FIG. 2C is a graph illustrating how the thickness T of the piezoelectric layer 12 affects the value of Q of a SAW resonator. The X-axis shows thickness T of the piezoelectric layer 12 in lambda. The Y-axis shows the ratio of QPAR to QNO-PAR in %, where QPAR is the Q when the parasitic conductance is present and QNO-PAR is the Q when the parasitic conductance is not present. If the thickness T of the piezoelectric layer 12 is more than 2×λ, Q is essentially unaffected. As can be seen in FIG. 2C, however, if T is less than 2×λ, Q becomes progressively degraded as T is reduced, due to the presence of the parasitic channel. FIG. 2C shows that, without a parasitic channel present, the value of Q would have remained constant regardless of the thickness of the piezoelectric layer 12.
Thus, the presence of the parasitic conductance causes the appearance of high conductivity paths that reduce the Q of the SAW resonators, which degrades the filter's performance. For SAW devices on bonded wafer 20, the piezoelectric layer 12 must have a thickness of at least 2×λ to avoid the creation of the parasitic conductance and the degradation of Q that is caused by the presence of the parasitic channel. Because the piezoelectric layer 12 of a bonded wafer 20 used for SAW filters must be at least 2λ thick, it is not possible to further reduce the thickness of the piezoelectric layer 12 in an effort to suppress the higher order modes in the piezoelectric film and to reduce the loss and thus enhance device performance.
Therefore, there is a need for a bonded wafer that resists the creation of a parasitic conductance at the top surface of the bulk silicon substrate during operation of the SAW filter so that a thinner piezoelectric layer may be used without degrading the performance of the SAW filter. One solution is to use a bonded wafer with low carrier lifetime in silicon.